To operate correctly, not only must the components of a semiconductor integrated circuit (IC) device be correctly designed, but the components must be capable of meeting the timing requirements of the circuit. Because ICs often operate at relatively high frequencies, if any of the individual components of the circuit exhibit excessive delay the device may fail to operate correctly. Accordingly, delays introduced by the individual components of the integrated circuit limit the maximum frequency of operation of the circuit.
In a device that includes a circuit having flip-flops and combinational logic, for example, the maximum speed of the device's system clock is limited by the setup and propagation delays of the flip-flops and the propagation delays of the combination logic incorporated into the device. To illustrate, FIG. 1 is a block diagram of a typical delay path in an integrated circuit. The delay path includes flip-flop 10 connected to flip-flop 12 through combination logic 14. In flip-flops 10 and 12, D represents a data input terminal, and Q represents a data output terminal. The terminal designated CK receives a clock signal that controls the operation of flip-flops 10 and 12.
As the clock signal cycles between states, flip-flop 10 releases data received on terminal D to combinational logic 14. This process introduces a first delay referred to as a flip-flop propagation delay (tp). After the data has been outputted by flip-flop 10 to combination logic 14, the data is processed by combinational logic 14, resulting in a combinational logic delay (tpcomb). Finally, combinational logic 14 supplies an output to flip-flop 12, which is set to a state based upon the value outputted by combinational logic 14. In order to capture the data from the combinational logic 14 correctly within flip flop 12, the data signal has to be established before the next clock positive edge. This required time margin is the set up time of the flip flop 12 (ts). Therefore, the total delay of the delay path shown in FIG. 1 is equal to the sum of the flip-flop propagation delay (tp), combinational logic delay (tpcomb), and the flip-flop setup time (ts). This delay, then, becomes a limiting attribute of the circuit as the frequency of the clock cycle of the circuit is constrained by the delay.
A number of factors can affect the delay of the components of an integrated circuit. During fabrication of the circuit, processing conditions can affect the performance of individual components of an integrated circuit. These processing conditions are difficult to control and can make it difficult to predict how delays will be manifested within the circuit during normal operations. Additionally, the operating voltage of the circuit, as well as the temperature of the circuit can affect delay within the circuit. This combination of factors can be referred to as the process, voltage, and temperature (PVT) factors.
Because is it difficult to predict or control the delays that may occur within an integrated circuit due to the PVT factors, designers are generally forced to design circuits to operate in worst-case scenarios (e.g., where the fabrication process, operating voltage, and ambient temperature result in significant delays occurring within the circuit). Designing for such a worst-case scenario may result in the device consuming too much power, or operating at an unnecessarily-high frequency. Either scenario is undesirable as it results in a circuit that is not performing optimally.